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Website Links:
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Here are a few of the websites and tools that we use and recommend.


Absolute Analysis
Developers and engineers choose Absolute Analysis Investigator™ protocol test solutions for their ease-of-use, flexibility, scalability, and versatility.

Apogee Applied Research
Provides engineering services and hardware systems to commercial and government end users.

Altera
Altera offers leading edge custom logic solutions, including FPGA's, CPLD's, and ASIC's.

Xilinx
Xilinx offers FPGA and CPLD solutions.

JPEG
Official site of the Joint Photographic Experts Group, JPEG.

sFPDP
The VITA website, home of the VITA 17.1 sFPDP standard.

Aldec
The best HDL design entry and simulation software we've seen. FPGA customers often fall into the starter version simulators packaged with the FPGA tools, but don't overlook Aldec. We use Aldec tools for all of our development, and recommend them to everyone. About Aldec...

Active-HDL™ Designer Edition
Active-HDL Designer Edition provides FPGA designers with a mixed RTL simulator that includes: industry proven IEEE mixed-language simulation support for VHDL, Verilog® and SystemVerilog (Design), with 2X-plus performance gains over FPGA supplied RTL simulators, encrypted IP support and no limitations on FPGA device size.
More Information: https://www.aldec.com/en/products/fpga_simulation/designeredition

Active-HDL™
Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL's Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs. The design flow manager evokes 120+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more.
More Information:
https://www.aldec.com/en/products/fpga_simulation/active-hdl
Evaluate Today! https://www.aldec.com/en/downloads/active-hdl

Riviera-PRO™
Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards..
More Information: https://www.aldec.com/en/products/functional_verification/riviera-pro
Evaluate Today! https://www.aldec.com/en/downloads/riviera-pro

ALINT-PRO™
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, avoiding problems on further design stages, clocks and reset tree issues, CDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
More Information: https://www.aldec.com/en/products/functional_verification/alint-pro
Evaluate Today! https://www.aldec.com/en/downloads/alint-pro

HES™
HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins. HES-DVM™ provides verification teams with multiple use modes including both emulation and physical prototyping techniques enabling SoC teams to work on a single platform.
More Information: https://www.aldec.com/en/products/emulation/hes-dvm

Aldec Order/Contact info: https://www.aldec.com/Company/Contact.aspx


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Absolute Analysis


Apogee Applied Research

 


Aldec



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