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Here are a few of the websites and tools that we use and recommend.
Developers and engineers choose Absolute Analysis Investigator™ protocol test solutions for their ease-of-use, flexibility, scalability, and versatility.
Apogee Applied Research
Provides engineering services and hardware systems to commercial and government end users.
Altera offers leading edge custom logic solutions, including FPGA's, CPLD's, and ASIC's.
Xilinx offers FPGA and CPLD solutions.
Official site of the Joint Photographic Experts Group, JPEG.
The VITA website, home of the VITA 17.1 sFPDP standard.
The best HDL design entry and simulation software we've seen. FPGA customers often fall into the starter version simulators packaged with the FPGA tools, but don't overlook Aldec. We use Aldec tools for all of our development, and recommend them to everyone. About Aldec...
Active-HDL™ Designer Edition
Active-HDL Designer Edition provides FPGA designers with an RTL simulator for less than $2,000 and includes: industry proven IEEE mixed-language simulation support for VHDL, Verilog® and SystemVerilog (Design), with 2X-plus performance gains over FPGA supplied RTL simulators, encrypted IP support and no limitations on FPGA device size.
Active-HDL is an integrated FPGA design and verification environment with a powerful mixed-language simulator and tools for graphical design entry, project management, HDL verification and documentation, providing an efficient (FPGA vendor-independent) environment for end-to-end design processing. A multi-vendor flow manager controls simulation, synthesis and implementation for all devices from Actel®, Altera®, Lattice®, Quicklogic®, Xilinx® and other FPGA vendors. A co-simulation interface to MATLAB® and Simulink® facilitates DSP designs. HDL language support: VHDL, Verilog®, EDIF, SystemC and SystemVerilog. Operating system support: Windows® XP and Vista 32/64 bit support.
More Information: http://www.aldec.com/en/products/fpga_simulation/active-hdl
Evaluate Today! http://www.aldec.com/en/downloads/active-hdl
Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC/C/C++, Assertions and EDIF. It supports System Level Verification with SystemC and SystemVerilog, Assertion-based Verification, Electronic System Level (ESL), Transaction Level Modeling (TLM) and STARC® based Linting. Riviera-PRO works in command line mode for maximum speed and includes enhanced editing, tracing, debugging capabilities and Code Coverage. Riviera-PRO is compatible with popular EDA products such as Synopsys® SmartModels™, SpringSoft®, Denali®, MATLAB® and Simulink®.
More Information: http://www.aldec.com/en/products/functional_verification/riviera-pro Evaluate Today! http://www.aldec.com/en/downloads/riviera-pro
ALINT is a VHDL and Verilog Design Rule Checking Tool used to analyze HDL source code against a comprehensive set of ASIC design guidelines for early bug detection. ALINT reduces risk when developing complex multi-million gate ASICs by resolving structural, coding and consistency problems early in the design cycle. ALINT delivers support for VHDL, Verilog and Mixed-Language designs, cross-probing between the source code and error messages, advanced rule configuration and result analysis.
More Information: http://www.aldec.com/en/products/functional_verification/alint
Evaluate Today! http://www.aldec.com/en/downloads/alint
HES-7 provides SoC/ASIC hardware verification and software validation teams with a scalable and high quality FPGA-based ASIC prototyping solution backed with an industry leading 1-year limited warranty.
More Information: http://www.aldec.com/en/products/prototyping/hes-7
Aldec Order/Contact info: http://www.aldec.com/Company/Contact.aspx