Serial FPDP sFPDP VITA 17.3 17.1 JPEG2000 Altera Xilinx Microsemi
Serial FPDP sFPDP VITA 17.3 17.1-2003 VITA 17.1-2015 Ethernet JPEG2000 Altera Xilinx Microsemi
Serial FPDP sFPDP VITA 17.3 VITA 17.1-2003 Ethernet JPEG2000 Altera Xilinx



StreamDSP is an intellectual property (IP) company specializing in high speed serial communications, Digital Signal Processing (DSP), and video processing for Altera, Xilinx, and Microsemi Field Programmable Gate Array (FPGA) devices. We have over 50 years of combined experience serving the military and commercial markets, and are now focusing our efforts on IP Core development and support. We can also work with our partner companies to offer design services in areas of Digital Signal Processing, Hardware and System Design, and Algorithm Development.

NEW!!! sFPDP-Gen3

Serial Front Panel Data Port Gen 3 is a VITA standard (VITA 17.3-2018) serial communications protocol for use in high bandwidth systems. VITA/ANSI 17.3 is the successor to the ANSI/VITA 17.1 standard and supports the same user data frame types and sync methods, allowing for easy upgrades from 17.1 to 17.3. The ANSI/VITA 17.3 standard was designed to be lightweight and low latency by using the same 64B/67B framing layer defined in the Interlaken v1.3 specification, providing over 95% bandwidth efficiency. Multi-lane channel bonding and automatic lane synchronization allow for unprecedented bandwidth scalability. Our sFPDP Gen 3 IP supports line rates up to 25Gbps (per lane) in modern FPGAs such as Startix-10 and Virtex UltraScale+.

Upgrade your VITA 17.1 based system to VITA 17.3 today !!!

See the sFPDP Gen3 product page for more details...


Serial Front Panel Data Port is a VITA standard (VITA 17.1-2015) serial communications protocol designed for maximum data throughput and low overhead. It offers both point-to-point and ring-based network topologies to support many different types of systems. Serial FPDP (sFPDP) can be unidirectional or bi-directional, and has support for flow control and error detection. Unlike Ethernet networks, an sFPDP data link has low latency and deterministic timing making it ideal for use in high bandwidth, timing critical systems. When implemented in an Altera, Xilinx, or Microsemi FPGA, sFPDP provides an unbeatable combination of bandwidth, flexibility, and ease of use.

See the sFPDP product page for more details...


Interlaken is a royalty-free interconnect protocol that was developed by Cisco Systems and Cortina Systems in 2006. The full Interlaken protocol (described in the Interlaken Protocol Specification, v1.2) was designed to support chip-to-chip packet transfers in high-bandwidth networking equipment. The low level Framing (PCS) layer of the Interlaken protocol offers many benefits as a stand-alone lightweight interconnect:
  • Channel bonding supported for any number of physical lanes
  • Any serial line rate supported by the FPGA transceiver can be used
  • Self-synchronizing links and automatic link resynchronization
  • Per-lane CRC32 for data integrity and diagnostics
  • Superb DC balancing for maximum link stability
  • Over 95% bandwidth efficient
The StreamDSP Interlaken-PHY IP core is an excellent choice for FPGA designers looking for an extremely efficient serial protocol for use as FPGA, backplane, or chassis interconnect that supports both Altera and Xilinx FPGAs. The scalability and high bandwidth of the Interlaken-PHY IP core also makes it an excellent choice for remote sensor applications.

See the Interlaken-PHY product page for more details...

10 Gigabit Ethernet

Our partner Apogee Applied Research offers a 10 Gigabit Ethernet Core. Unlike other 10GbE cores, the Apogee 10GbE Core offers a full FPGA hardware-based implementation for the Physical (10GbSFP+), Link (Ethernet, ARP), Internet (IPv4,IGMP), and Transport (UDP) layers. The FPGA Ethernet processor uses a dual proprietary microcoded Finite State Machine (FSM) to process the incoming and outgoing packets. The FSMs are connected for handling of automated response packets such as ARP and IGMP. Each FSM contains a large 512 entry table for storage and high-speed search of the possible packet addresses. The address table contains the MAC address, VLAN, IP, and UDP port. The processor supports multicast using IPv4 and IGMPv2 and IGMPv3.
Apogee also offers other IP related to Software Defined Radio (SDR) processing, Multi-Channel CIC filters, and Ethernet Packet Switching.

See the Apogee Applied Research website for more details...


JPEG2000 is a video compression and decompression standard optimized for the highest quality of video and still images possible. JPEG2000 offers both lossy and lossless compression in a single codestream, making it a perfect choice for both high quality and high compression rate applications. JPEG2000 is used in commercial applications, medical and satellite imagery, video recording, and has been selected by the Motion Picture Association of America (MPAA) for use in digital cinema. JPEG2000 has also becoming a popular choice in military applications in recent years. The National Imagery Transmission Format Standard (NITFS) is a U.S. Department of Defense (DoD) and Federal Intelligence Community (IC) suite of standards for the exchange, storage, and transmission of digital-imagery products and image-related products. NITF has adopted the ISO/IEC 15444-1 (JPEG2000) standard for imagery compression. In addition, JPEG2000 video streams can easily be transmitted with our VITA 17.1 Serial FPDP (sFPDP) serial communication IP to create efficient and scalable video compression solutions.

See the JPEG2000 product page for more details...

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