The release of version 4.3 of the StreamDSP VITA 17.1 Serial Front Panel Data Port (sFPDP) IP core has been announced by StreamDSP, enabling support for the latest 28nm FPGA devices from Altera and Xilinx.
COLUMBUS, OH (PRWEB) NOVEMBER 01, 2012
The StreamDSP sFPDP IP core is a fully-compliant implementation of the Serial Front Panel Data Port (sFPDP) communications standard, as defined by the VITA specification. With its latest release, StreamDSP has added support for new 28nm Altera and Xilinx FPGA devices. The following FPGA devices have now been fully verified and hardware tested with the StreamDSP sFPDP IP Core:
Altera Stratix-V GX, Stratix-IV GX, and Stratix-II GX
Altera Arria-II GX and Arria GX
Xilinx Virtex-7, Virtex-6 LXT, Virtex-5 LXT/FXT, and Virtex-4 FX
Xilinx Spartan-6 LXT
StreamDSP provides “ready-to-run” simulations, evaluations, and reference designs targeted to popular development boards for each of the supported FPGA families. This allows StreamDSP’s customers to quickly and easily verify proper operation both in simulation and on their chosen device family and greatly shorten integration time. The wide range of FPGA device support also allows StreamDSP to do extensive compatibility testing between different FPGA families using their own array of development boards, third party sFPDP based equipment, and a Serial FPDP protocol analyzer from Absolute Analysis.
“Our Serial FPDP IP core has become very popular with both commercial and military customers over the past few years,” commented Greg Schueller, StreamDSP’s Director of Business Development. “We are committed to providing our customers with a solid, reliable product backed by excellent support. We have a solid, global customer base and we continue to see our number of direct referrals grow each year. We will continue to support this IP, add new FPGA device families as they become available, and add additional features to this IP for many years to come,” added Greg.
To support the growing number of requests for even higher bandwidth, StreamDSP now provides a multi-lane wrapper that can be used to channel-bond several sFPDP lanes together. Rather than the traditional PCS or protocol-level channel bonding, StreamDSP’s wrapper channel bonds independent sFPDP lanes together at the user FIFO level. This gives StreamDSP’s customers access to very high-bandwidth multi-lane data paths. In addition, StreamDSP is currently leading the VITA 17.2 working group to define the next generation of the sFPDP standard which plans to support rates up to 10Gbps as well as true protocol-level channel bonding.
Greg Schueller, Director of Business Development
Tel. +1 (855) DSP-FPGA
Fax. +1 (855) 377-3742
StreamDSP LLC, 1275 Kinnear Rd, Columbus, OH, 43212, USA
More information about the Serial FPDP VITA 17.1 Standard can be found at https://www.vita.com
Information on Absolute Analysis is available at https://www.absoluteanalysis.com
For more specific information about StreamDSP’s IP products, please visit: https://www.streamdsp.com, or call (855) 377-3742.
About StreamDSP LLC
StreamDSP is an intellectual property (IP) company specializing in video, serial communications, and data storage solutions for Field Programmable Gate Array (FPGA) devices. Headquartered in Columbus, OH, StreamDSP has over 50 years of combined experience serving the military and commercial markets, and is focused on developing IP and providing custom design services for FPGAs.
Read the original post here: https://www.prweb.com/releases/streamdsp/sfpdp/prweb10076529.htm